Semiconductor packaging is used to protect an integrated circuit (e.g., microprocessor, microcontroller, ASIC device, sensor, power transistor, etc.) and to provide an electrical and thermal interface between the integrated circuit and an external component, such as a printed circuit board. Typically, a semiconductor package is designed to protect the integrated circuit from potentially damaging environmental conditions, such as extreme temperature variations, moisture, dust particles, etc. In addition, the semiconductor package includes external terminals (e.g., leads, pads, etc.) that provide an electrical interface between the terminals of the integrated circuit and the external component.
A variety of different package types have been developed as the semiconductor industry has evolved. One of the first package types developed was the so-called TO (transistor outline) package, which encapsulates a single semiconductor die, such as a transistor or diode, and includes two or three leads directly extending out of the encapsulant portion. One package type that followed the TO package is the so called DIP (dual in-line package), which offers a higher lead count and more I/O capability than the TO package. One package type that followed the DIP package is the so-called QFP (quad-flat-package), which offers a high lead count due to the provision of “gull wing” style leads on each of the four sides of the package. From there, so-called surface mount packages evolved. Surface mount packages include flat pads instead of leads, and therefore reduce space. An example of a surface mount package is a BGA (ball grid array), which features a grid array of solder balls on a bottom side of the package that are used to provide external electrical terminals.
To date, there are a large number of standard package types that are commercially available and widely used. Examples of these package types include the DIP (dual in-line package), LGA (land grid array), MCM (multi-chip module), LCC (leaded chip carrier), PGA (pin grid array), CFP (ceramic flat pack), QFN (quad flat no-leads), TSOP (thin small-outline package) and WLB (Wafer Level Ball Grid Array). There is substantial diversity in the internal construction of these packages and substantial variation in the processes used to make any one of these package types. Wiring techniques can vary (e.g., wire bonding, solder bump, thin film attach, etc.). Encapsulation techniques can vary (e.g., transfer molding, compression molding, lamination, etc.). The driving factors that motivate one to select package types and process techniques over another include cost, electrical performance, thermal performance, interconnect density, system integration capability and reliability. Typically, in the life cycle of a product, performance is initially the most important consideration, but as the product phases through its life cycle, cost becomes the dominant factor.
One approach to reducing package assembly cost is to utilize parallel processing techniques. Parallel processing refers to a technique whereby the same packaging process (e.g., wire bonding, die attach, encapsulation, etc.) is performed on multiple packaging sites simultaneously. An example of this technique involves using a lead-frame strip with a high number of identical unit cells (e.g., 10, 20, 50, etc.), with each unit cell having the lead construction of the desired package type. The lead frame strips are loaded into various packaging tools (e.g., a die attach tool, a molding tool, a lead trimming tool, etc.) and package processing is applied to each unit cell in the lead-frame strip simultaneously. Eventually, the unit lead frames are singulated and a number of identical packages are produced.
To date, package assembly lines are built to produce a single package type (e.g., CFP, QFN, TSOP etc.) Each package assembly line requires investment, planning, build of materials, flow design, tooling, and a manufacture location that is dedicated to producing only one type of package. These factors lead to increased cost for each package.